DFT Design Engineer -Memory Team

Job Detail

Position Summary

Roles and Responsibilities:

Good Experience in Top/Block, FLAT/Heir DFT insertion flow methodologies
Executed scan & MBIST insertion, ATPG and verification at full chip level
Experience in timing closure in DFT modes – understanding of shift, capture timing constraints, MBIST constraints and their impacts
Generate, review and validate DFT constraints to achieve timing closure of high speed design
Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations)
Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification
Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests
Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved
Understanding of Power Estimation/Management for DFT modes is preferred
Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples
Strong written and oral communication skills

Experience:

5+ Years

Qualifications

B.Tech / B.E / M.Tech / M.E

Role:
Product Design Engineer

Industry Type:
Electronic Components / Semiconductors

Department:
Engineering – Hardware & Networks

Employment Type:
Full Time, Permanent

Role Category: Hardware

Education:

UG:
B.Tech / B.E. in Production/Industrial

PG:
M.Tech in Electronics/Telecommunication